1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and more particularly to a semiconductor device comprising a multi-layered interconnection that is formed by the damascene method and a manufacturing method thereof.
2. Description of the Related Art
In recent years, accompanying the progress in technology to attain higher integration of the semiconductor device and smaller chip size, further miniaturization of the interconnection and wider application of multi-layered interconnection have been being made, and, as the method of forming the multi-layered interconnection structure, there has become in wide use what is called the damascene process wherein the interconnection or the via plug is formed by filling up the interconnection trench or the via hole with Cu and then applying the planarization by the CMP (Chemical Mechanical Polishing) method thereto. Although this damascene process certainly enables the interconnections to be spaced densely, the interconnections once placed close to one another may bring about a problem of signal delay owing to the parasitic capacitances between these interconnections. In order to overcome the problem of this signal delay, the reduction of the interconnection capacitance is, therefore, a matter of great importance.
As the method of reducing the interconnection capacitance, the method in which a material with a low dielectric constant is utilized for the interlayer insulating film, in place of a conventional SiO2-based insulating film, has been much investigated. Now, referring to the drawings, a conventional damascene process wherein a low-dielectric-constant film is employed as an interlayer insulating film is described. FIGS. 11 and 12 are schematic cross-sectional views illustrating, in sequence, the steps of a conventional damascene method.
First, as shown in FIG. 11(a), after a first barrier film 2 and a first interlayer insulating film 3 are grown, in succession, on a substrate 1, coatings of an anti-reflection film and a photoresist are successively applied onto the first interlayer insulating film 3 and, then, the exposure and the development are performed to form a resist pattern (not shown in the drawings), and with this resist pattern being used as a mask, a first interconnection trench is formed by a known technique of dry etching. Next, after the resist pattern and the anti-reflection film are removed by means of oxygen ashing, depositions of a first barrier metal 4 and Cu are applied thereto and, then, by removing portions of the first barrier metal 4 and Cu overlaid the first interlayer insulating film 3, a lower layer interconnection 5 is formed.
Next, as shown in FIG. 11(b), on this lower layer interconnection 5, a second barrier film 6 of SiCN that prevents the Cu diffusion and acts as an etching stopper in the via hole formation and a second interlayer insulating film 7 made of a film of a low-dielectric-constant material such as SiOC, hydrogen silsesquioxane (referred to as HSQ hereinafter) or methyl silsesquioxane (referred to as MSQ hereinafter) are grown in succession. After that, coatings of an anti-reflection film and a photoresist are successively applied onto the second interlayer insulating film 7 and, then, the exposure and the development are performed to form a resist pattern (not shown in the drawings) for the formation of a via hole 7a, and with this resist pattern being used as a mask, a second interlayer insulating film 7 is etched by a known technique of dry etching. Next, after the resist pattern and the anti-reflection film are removed by means of oxygen ashing, the second barrier film 6 is etched by etch back to form a via hole 7a to run through the second interlayer insulating film 7 and the second barrier film 6.
Next, as shown in FIG. 11(c), depositions of a second barrier metal 8 that is to be used as a base for the interconnection material and Cu 9a are applied thereto and thereafter, as shown in FIG. 11(d), portions of the second barrier metal 8 and the Cu 9a overlaid the second interlayer insulating film 7 are removed, and thereby a via plug 9 connecting with the lower layer interconnection 5 is formed.
After that, in the same way as described above, a third barrier film 10 and a third interlayer insulating film 11 are grown thereon, and, using known techniques of photolithography and dry etching, a second interconnection trench 11a is formed (See FIG. 12(a)), and then, after depositions of a third barrier metal 12 and Cu 13a are made (See FIG. 12(b)), portions of the third barrier metal 12 and the Cu 13a overlaid the third interlayer insulating film 11 are removed by the CMP method to form an upper layer interconnection 13 (See FIG. 12(c)). A semiconductor device with a prescribed multi-layered interconnection structure may be fabricated by performing these steps repeatedly.
In such a damascene process, the barrier film must perform not only a function of preventing Cu in an underlying interconnection or via plug from diffusing out into its overlying interlayer insulating film but also a function of acting as an etching stopper when a via hole or an interconnection is subsequently formed in that overlying interlayer insulating film. If, for example, the second barrier film 6 cannot perform as the etching stopper satisfactorily, when the second interlayer insulating film 7 is etched in the step of FIG. 11(b), the etching without being stopped by the second barrier film 6 proceeds to expose the lower layer interconnection 5, and, as a result, in the oxygen ashing which is carried out to remove the resist pattern, the surface of the lower layer interconnection 5 may be oxidized, and the faulty connection between the lower layer interconnections 5 and the via plug 9 may be brought about. To overcome the above problem, it is essential for the barrier film to provide a high etching selection ratio of the overlying interlayer insulating film thereto and, from this viewpoint, a material such as SiC, SiN or SiCN is generally employed.
Further, regarding the deposition of the barrier film with SiN, for example, in Japanese Patent Application Laid-open No. 9150/2002, there is set a problem that, as the deposition temperature of SiN is 400° C. or so, Cu becomes more liable to aggregate and the homology of the Cu surface may deteriorate, with rising the substrate temperature. One of the methods to suppress the Cu aggregation is obviously setting the deposition temperature lower, but if the deposition temperature is set low, the film of SiN may become an insulating film of low density, which cannot provide a satisfactory etching selection ratio of the interlayer insulating film of SiO2 or such. Accordingly, in the above publication, it is disclosed that a barrier film (a Cu-diffusion preventive insulating film) is made to have a layered structure composed of a first insulating film grown at a low temperature below 350° C. by the CVD (Chemical Vapor Deposition) method and a second insulating film grown at a high temperature in a range of 350° C. to 450° C. inclusive by the CVD method, and, therein, the Cu aggregation is suppressed by making the deposition temperature of the film on the side of the interconnection low, while the drop of the etching selection ratio is prevented by making the deposition temperature of the film on the side of the interlayer insulating film high.
Further, when a low-dielectric-constant film is used as an interlayer insulating film, it is required to lower the dielectric constant of the barrier film as well so that the parasitic capacitance between the interconnections may be reduced. The dielectric constant of the SiN-based barrier film is considerable high, and when a fluorine-containing film of SiOF or such is used as the underlying interlayer insulating film and this film is subjected to the plasma etching, the SiN-based film may be damaged by fluorine radicals produced in that etching. Meanwhile, the SiC-based barrier film may have advantages of the excellent etching selection ratio and the low dielectric constant in the region of 5 but also disadvantage of the insufficient capability to prevent the Cu diffusion. Accordingly, there are disclosed, in Japanese Patent Application Laid-open No. 83869/2002, a structure wherein, on an interlayer insulating film (a first insulating layer) with a low dielectric constant where a trench or a hole is set, there is formed a second insulating layer whose main constituent elements are Si, C and N, wherein the ratio of the number of C atoms to the number of Si atoms is set to be 0.2 to 0.8 and the ratio of the number of N atoms to the number of Si atoms is set to be 0.15 to 1.0; and further in Japanese Patent Application Laid-open No. 83870/2002, another structure wherein a second insulating layer contains 1021 to 1022 (cm−3) carbon-hydrogen bond containing groups (CHn groups), whereby both the low dielectric constant and the high etching selection ratio may be attained.
Nevertheless, in the art described in Japanese Patent Application Laid-open No. 9150/2002, only the functions of preventing the Cu diffusion and acting as the etching stopper are considered as the functions necessary for the barrier film, and the dielectric constant is not taken into account, at all. In consequence, even if the low-dielectric-constant film is used as the interlayer insulating film, the barrier film may increase the overall dielectric constant so that a problem that the interconnection capacitance cannot be reduced sufficiently may remain.
Further, in Japanese Patent Application Laid-open No. 83869/2002 and Japanese Patent Application Laid-open No. 83870/2002, it is described that the SiCN-based insulating film that is set to overlie the interlayer insulating film and act as an etching stopper in each structure can provide a high etching selection ratio of the underlying interlayer insulating film thereto, a low dielectric constant as well as an excellent function of making the metal diffusion low. However, in the case of the SiCN-based insulating film, when its C content becomes larger, the etching selection ratio falls, but when its C content becomes smaller, its dielectric constant increases so that the reduction of the interconnection capacitance cannot be achieved. In effect, the structures described in these publications cannot provide the rise of the etching selection ratio and the reduction of the dielectric constant, simultaneously.
Further, for the barrier film, in addition to the above functions, it is essential to have good adhesiveness to Cu that is an interconnection material. Unless the adhesion between Cu and the barrier film is kept well, Cu atoms on the interconnection surface become liable to move, giving rise to a problem of deterioration of the electromigration resistance. Yet, in the above publications, the adhesiveness between Cu and the barrier film is not taken into consideration, at all.
In short, in the damascene method wherein the Cu interconnection is formed by the CMP method, it is important for the barrier film formed between the Cu interconnection and its overlying interlayer insulating film to meet the following four demands; that is, 1. the etching selection ratio of the interlayer insulating film thereto should be high; 2. the Cu diffusion should be prevented with effect; 3. the dielectric constant should be low; and 4. it should adhere well to the Cu interconnection, and a new proposal for the barrier film capable to satisfy all these demands has been long waited for.
In light of the above problems, the main object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.